1. Field of the Invention
This invention relates to an echo canceler and to an operating method therefor.
2. Description of Related Art
In long-distance telephone lines, part of the reception signal output from the sending party""s end passes through a two-wire-to-four-wire conversion hybrid (or echo path) on the receiving party""s end and circles back to the sending party, resulting in an echo which interferes significantly with the call. One apparatus for preventing this is a conventional echo canceler. One example of such an echo canceler is disclosed in Japanese Patent Application Laid-Open No. H9-93088/1997.
FIG. 27 is a configuration diagram for an echo canceler disclosed in the cited literature.
This echo canceler 100 comprises an adaptive filter modulus computing system 102, and adaptive filter 104, and an adder 106. The adaptive filter modulus computing system 102 produce an adaptive filter modulus Hm(i) for eliminating an echo E(i) that comes back with a delay to the sender""s side SS. The adaptive filter 104, using that adaptive filter modulus Hm(i), produces a pseudo-echo signal GE(i) for that echo E(i). The adder 106 subtracts the pseudo-echo signal GE(i) from the echo E(i) to eliminate the echo E(i). Accordingly, the power of the echo component in the voice of the receiving party that comes back after a delay to the receiving side RS is reduced.
The symbol i (i=1, 2, 3, . . . ) represents a sample number for each signal. For example, the reception signal X(i) for the sample number 2 becomes X(2). The symbol m (m=1, 2, 3, . . . ) is a number (or convolution number) associated with each of a plurality of the delayers (or tap devices) that configure the adaptive filter modulus computer (described below) contained in the adaptive filter modulus computing system 102. For example, the adaptive filter modulus Hm(i) for the sample number 3 in the delayer having the number 5 becomes H5(3).
A concrete description is now given for the operation of the adaptive filter modulus computing system 102, the adaptive filter 104, and the adder 106.
This adaptive filter modulus computing system 102 only operates when the call status is in a simplex status, that is, when a reception signal X(i) directed toward the receiving party""s side RS by the sending party exists, but no transmission signal exists that is directed toward the sending party""s side SS by the receiving party. This adaptive filter modulus computing system 102 estimates the delay characteristics (that is, impulse response in the echo path) of the two-wire-to-four-wire conversion hybrid HB at the receiving party""s side RS by a commonly known least mean square method (hereinafter LMS method). That estimated impulse response becomes the adaptive filter modulus Hm(i) described above. With the LMS method, the power of the echo cannot be reduced to or below the noise level. A method for resolving this problem is disclosed in the prior art literature cited earlier. Specifically, this adaptive filter modulus computing system 102 computes the adaptive filter modulus Hm(i) according to formula 16 or formula 17 below, each of which is a computation formula in the LMS method.                                                                                                               A                    m                                    ⁢                                      xe2x80x83                                    ⁢                                      (                    i                    )                                                  =                                                      ∑                                          j                      =                                                                        iBL                          ⁢                                                      xe2x80x83                                                    ⁢                                                      (                            i                            )                                                                          +                        1                                                                                                            (                                                  i                          +                          1                                                )                                            ⁢                      BL                      ⁢                                              xe2x80x83                                            ⁢                                              (                        i                        )                                                                              ⁢                                      xe2x80x83                                    ⁢                                      ER                    ⁢                                          xe2x80x83                                        ⁢                                          (                      j                      )                                        ⁢                                          xe2x80x83                                        ⁢                    X                    ⁢                                          xe2x80x83                                        ⁢                                          (                                              j                        -                        m                                            )                                                                                                                                                                XP                  m                                =                                                      ∑                                          i                      =                      1                                        T                                    ⁢                                      xe2x80x83                                    ⁢                                      (                                                                  ∑                                                  j                          =                                                                                    iBL                              ⁢                                                              xe2x80x83                                                            ⁢                                                              (                                i                                )                                                                                      +                            1                                                                                                                                (                                                          i                              +                              1                                                        )                                                    ⁢                          BL                          ⁢                                                      xe2x80x83                                                    ⁢                                                      (                            i                            )                                                                                              ⁢                                                                        X                          2                                                ⁢                                                  xe2x80x83                                                ⁢                                                  (                                                      j                            -                            m                                                    )                                                                                      )                                                                                                                                                                R                    m                                    ⁢                                      xe2x80x83                                    ⁢                                      (                    i                    )                                                  =                                                                            A                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                                            XP                    m                                                                                                                                                                H                    m                                    ⁢                                      xe2x80x83                                    ⁢                                      (                                          i                      +                      1                                        )                                                  =                                                                            H                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                        +                                                            KR                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                                                                          }                            (        16        )                                                                                                                          A                    m                                    ⁢                                      xe2x80x83                                    ⁢                                      (                    i                    )                                                  =                                                      ∑                                          j                      =                                                                        iBL                          ⁢                                                      xe2x80x83                                                    ⁢                                                      (                            i                            )                                                                          +                        1                                                                                                            (                                                  i                          +                          1                                                )                                            ⁢                      BL                      ⁢                                              xe2x80x83                                            ⁢                                              (                        i                        )                                                                              ⁢                                      xe2x80x83                                    ⁢                                      ER                    ⁢                                          xe2x80x83                                        ⁢                                          (                      j                      )                                        ⁢                                          xe2x80x83                                        ⁢                    X                    ⁢                                          xe2x80x83                                        ⁢                                          (                                              j                        -                        m                                            )                                                                                                                                                                                    XP                    m                                    ⁡                                      (                    i                    )                                                  =                                                      ∑                                          j                      =                                                                        iBL                          ⁢                                                      xe2x80x83                                                    ⁢                                                      (                            i                            )                                                                          +                        1                                                                                                            (                                                  i                          +                          1                                                )                                            ⁢                      BL                      ⁢                                              xe2x80x83                                            ⁢                                              (                        i                        )                                                                              ⁢                                                            X                      2                                        ⁢                                          xe2x80x83                                        ⁢                                          (                                              j                        -                        m                                            )                                                                                                                                                                                    R                    m                                    ⁢                                      xe2x80x83                                    ⁢                                      (                    i                    )                                                  =                                                                            A                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                                                                  XP                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                                                                                                                                                    H                    m                                    ⁢                                      xe2x80x83                                    ⁢                                      (                                          i                      +                      1                                        )                                                  =                                                                            H                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                        +                                                            KR                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                                                                          }                            (        17        )            
In these formulas 16 and 17, ER(i) represents the echo remainder, that is, the difference between the echo E(i) and the pseudo-echo signal GE(i). This echo remainder ER(i) is the echo component that cannot be eliminated, and hence remains, even after subtracting the pseudo-echo signal GE(i) from the echo E(i). Rm(i) is the modulus update amount. K (K greater than 0) is the step gain. BL(i) is the block length (or number of computation terms). T is the number of delayers (or tap devices) contained in the adaptive filter modulus computing system 102 that are used. This number used is called the tap length T, and is preset. The maximum value of this tap length T is the total number of delayers.
The parameters for the adaptive filter modulus Hm(i) described in the foregoing are the echo remainder ER(i), the reception signal X(i), and the block length BL(i). Of these parameters, the echo remainder ER(i) and reception signal X(i) are both observed values, while the block length BL(i) is an artificial parameter.
The method of determining the block length BL(i) is now described.
The adaptive filter modulus computing system 102 described in the foregoing compares the size relationship between the modulus update amount in the formulas 16 and 17 and the Rm(i) after one sample from that modulus update amount Rm(i), and thereby determines the block length BL(i) which it outputs to the adaptive filter 104.
Now, according to the LMS method, by producing a pseudo-echo signal GE(i) using the adaptive filter modulus Hm(i) produced according to formulas 16 and 17, and subtracting that pseudo-echo signal GE(i) from the echo E(i), the power of the echo remainder ER(i) is reduced to the level of the power of the noise N(i). This noise N(i), however, is assumed not to contain an echo component.
According to formula 16 or formula 17, when the modulus update amount is Rm(i+1)xe2x89xa6Rm(i), Hm(i) converges. When this happens, this adaptive filter modulus computing system 102 estimates that the power of the echo remainder ER(i) can be reduced to the level of the noise N(i) power, and, based on that decision, holds the block length BL(i).
When the modulus update amount is Rm(i+1) greater than Rm(i), the adaptive filter modulus Hm(i) diverges. When that happens, the adaptive filter modulus computing system 102 described earlier estimates that the power of the echo remainder ER(i) cannot be reduced to the level of the noise N(i) power, and, based on that decision, lengthens the block length BL(i).
This adaptive filter modulus computing system 102, however, does not lengthen the block length BL(i) using the block length BL(i) at that current point in time as a reference value, but sequentially lengthens it from the predetermined minimum value of the block length. For example, if the current block length BL(i) is 30 and the modulus update value Rm(i+1) greater than Rm(i), this block length BL(i) will first return from 30 to the minimum value (10, for example) of the block length BL(i). Next, this adaptive filter modulus computing system 102 starts increasing that block length BL(i) at a constant ratio (adding 1 at a time, for example), from that minimum value. This computation of the modulus update amount Rm(i) by lengthening the block length BL(i) is continued until Rm(i+1)xe2x89xa6Rm(i).
Next, the adaptive filter 104 described earlier produces a pseudo-echo signal GE(i) for the echo E(i) that circles back to the sending party""s side SS, using formula 3 below. That is, the adaptive filter 104 produces the pseudo-echo signal GE(i) by convoluting the reception signal X(i) with the adaptive filter modulus Hm(i) output from the adaptive filter modulus computing system 102, and outputs that to the adder 106.                               GE          ⁢                      xe2x80x83                    ⁢                      (            i            )                          =                              ∑                          m              =              1                        T                    ⁢                      xe2x80x83                    ⁢                                    H              m                        ⁢                          xe2x80x83                        ⁢                          (              i              )                        ⁢                          xe2x80x83                        ⁢            X            ⁢                          xe2x80x83                        ⁢                          (                              i                -                m                            )                                                          (        3        )            
Next, that adder 106 subtracts the pseudo-echo signal GE(i) from the echo E(i) and thereby weakens the power of the echo E(i).
By repeating the process described in the foregoing, according to the LMS method, the power of the echo remainder can theoretically be lowered to the noise power from formula 3 and either formula 16 or formula 17.
However, the echo canceler 100 described in the foregoing is subject to a number of problems as discussed below.
First Problem: According to the known LMS method described in the foregoing, the power of the echo remainder ER(i) cannot theoretically be lowered below the level of the noise N(i) power.
Second Problem: Even with prior art that remedies the problems with the LMS method, moreover, the power of the echo remainder ER(i) cannot always be lowered to the level of the noise N(i) power. This is due to the following main causative factors:
(1) amplitude of noise N(i) fluctuates greatly;
(2) impulse response in echo path fluctuates; and
(3) tap length T is inadequate.
Thus the call is interfered with because the power of the echo remainder ER(i) is greater than the power of the noise N(i).
Third Problem: According to the echo canceler 100 having the conventional configuration described in the foregoing, moreover, when the modulus update amount Rm(i+1) greater than Rm(i), the block length BL(i) is sequentially lengthened with a constant ratio from the predetermined minimum value, following formula 16 or 17 given earlier, until the modulus update amount becomes such that Rm(i+1)xe2x89xa6Rm(i) As a consequence, the computation volume for updating the modulus update amount Rm(i) becomes significantly larger. Accordingly, much time is required to determine the block length BL(i), resulting in the shortcoming that much time is required to determine the adaptive filter modulus Hm(i). This also involves the shortcoming of the power consumption becoming high.
Fourth Problem: According to the echo canceler 100 having the conventional configuration described in the foregoing, moreover, the block length BL(i) is only computed when the call status is simplex. Hence when the call status changes to the simplex status from any call status other than the simplex status, this echo canceler 100 must again redo the block length BL(i) computation beginning from the predetermined minimum value. As a result, in the simplex status, much time is required to determine the block length BL(i), resulting in the shortcoming that much time is required to determine the adaptive filter modulus Hm(i) This also involves the shortcoming of the power consumption becoming high.
Thereupon, an object of the present invention is to provide an echo canceler capable of lowering the power of the echo remainder below the level of the noise power in order to resolve the first problem.
Another object of the present invention is to provide an echo canceler capable of lowering the power of the echo remainder to the level of the noise power, even when the noise amplitude fluctuates greatly, even when the impulse response in the echo path fluctuates, and even when the tap length is inadequate, in order to resolve the second problem.
Yet another object of the present invention is to provide an echo canceler that performs simple computations in deriving the adaptive filter modulus, in order to resolve the third problem.
Yet another object of the present invention is to provide an echo canceler that estimates the block length when the call status is other than the simplex status, and utilizes that estimated block length when the call status is changed from that non-simplex status to the simplex status, in order to resolve the fourth problem.
In order to attain these objects, the echo canceler of the present invention comprises a unique configuration that is described below. That is, the echo canceler of the present invention comprises an adaptive filter modulus computing system, adaptive filter, and adder for eliminating the echo produced when part of the reception signal output from the sending party side in a telephone line circles around to that sending party side via an echo path on the receiving party side.
With this invention, the adaptive filter modulus computing system estimates the echo path impulse response by the least mean square method, and outputs that estimated impulse response as the adaptive filter modulus. The adaptive filter convolutes the adaptive filter modulus and the reception signal and thereby produces, and outputs, a pseudo-echo signal for the echo. And the adder subtracts the pseudo-echo signal from the echo, thereby eliminating that echo.
With this invention, moreover, the adaptive filter modulus computing system described above comprises a duplex detector, block length determinator, and adaptive filter modulus computer.
With this invention, the difference between the echo and the pseudo-echo signal is made the echo remainder, the logarithmic ratio between the power of the reception signal and the power of the echo remainder is made the echo attenuation amount, and any predetermined target value for that echo attenuation amount is made the desired echo attenuation amount. The duplex detector noted above determines what the call status is, whether the simplex status, duplex status, call-transmission status, or non-calling status.
With this present invention, furthermore, when the call status has been determined by the duplex detector to be the simplex status, the block length determinator determines the block length in the least mean square method, and outputs it, so that the echo attenuation amount is finally made to be equal to or greater than the desired echo attenuation amount. The adaptive filter modulus computer then computes the adaptive filter modulus, using the block length, the echo remainder, and the reception signal, and outputs that adaptive filter modulus to the adaptive filter.
According to the configuration of this invention, when the duplex detector has determined that the call status is the simplex status, the echo attenuation amount can be made equal to or greater than the desired echo attenuation amount. That desired echo attenuation amount can be preset to any value. Accordingly, if, for example, the desired echo attenuation amount is set so that it is larger than the logarithmic ratio between the reception signal power and the noise power, the echo remainder power can be lowered below the level of the noise power.
In embodying this invention, it is preferable that, if in sample number i (i=1, 2, 3, . . . ) the reception signal be made X(i), the echo remainder be made ER(i), the m""th (m=1, 2, 3, . . . ) adaptive filter modulus be made Hm(i), and the block length be made BL(i), then, when the duplex detector has determined that the call status is the simplex status, the adaptive filter modulus computer be configured so that it computes the adaptive filter modulus Hm(i) according to formula 1 below (where xcex4P is a smoothing constant within the range 0 less than xcex4P less than 1, and K (K greater than 0) is the step gain).                                                                                                               A                    m                                    ⁢                                      xe2x80x83                                    ⁢                                      (                    i                    )                                                  =                                                      ∑                                          j                      =                                                                        iBL                          ⁢                                                      xe2x80x83                                                    ⁢                                                      (                            i                            )                                                                          +                        1                                                                                                            (                                                  i                          +                          1                                                )                                            ⁢                      BL                      ⁢                                              xe2x80x83                                            ⁢                                              (                        i                        )                                                                              ⁢                                      xe2x80x83                                    ⁢                                      ER                    ⁢                                          xe2x80x83                                        ⁢                                          (                      j                      )                                        ⁢                                          xe2x80x83                                        ⁢                    X                    ⁢                                          xe2x80x83                                        ⁢                                          (                                              j                        -                        m                                            )                                                                                                                                                                XP                  m                                =                                                                            (                                              1                        -                                                  δ                          p                                                                    )                                        ⁢                                          xe2x80x83                                        ⁢                                          XP                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                                              i                        -                        1                                            )                                                        +                                                            δ                      p                                        ⁢                                          xe2x80x83                                        ⁢                                          X                      2                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                                                                                                                                                    R                    m                                    ⁢                                      xe2x80x83                                    ⁢                                      (                    i                    )                                                  =                                                                            A                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                                                                  XP                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                                                                                                                                                    H                    m                                    ⁢                                      xe2x80x83                                    ⁢                                      (                                          i                      +                      1                                        )                                                  =                                                                            H                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                        +                                                            KR                      m                                        ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                                                                          }                            (        1        )            
According to this configuration of this invention, XPm(i) is approximately smoothed as a recurrence formula. Accordingly, compared to the XPm(i) formula in the conventional configuration, the computation volume and memory volume required to derive this XPm(i) are sharply reduced. Accordingly, the adaptive filter modulus Hm(i) can be simply derived.
In embodying this invention, moreover, it is preferable that, when the noise is made a noise component that excludes the echo component, the logarithmic ratio between the echo power and the echo remainder power is made the echo cancellation amount, and the logarithmic ratio between the echo power and the noise power is made the echo/noise ratio, the block length determinator comprises an echo attenuation amount computer, a desired echo attenuation amount indicator, an echo cancellation amount computer, an echo/noise comparison unit, a block length computer, and a block length controller.
When the duplex detector has determined that the call status is the simplex status, the echo attenuation amount computer noted above computes and outputs the echo attenuation amount. The desired echo attenuation amount indicator noted above indicates the desired echo attenuation amount. The echo cancellation amount computer computes and outputs the echo cancellation amount. And the echo/noise comparison unit computes and outputs the echo/noise ratio.
The block length computer noted above, based on the echo attenuation amount, desired echo attenuation amount, echo cancellation amount, and echo/noise ratio, computes and outputs the block length so that the echo attenuation amount is made equal to or greater than the desired echo attenuation amount.
From that block length, the block length controller noted above determines the block length to be output to the adaptive filter modulus computer and outputs that block length to the adaptive filter modulus computer.
In embodying this invention, it is preferable that the echo/noise comparison unit comprise an echo power computer, a noise power computer, and an echo/noise ratio computing unit. The echo power computer computes and outputs the echo power. The noise power computer computes and outputs the noise power. The echo/noise ratio computing unit computes, and then outputs, the echo/noise ratio from the echo power output by the echo power computer and the noise power output by the noise power computer.
As according to a preferable embodiment of this invention, moreover, the echo canceler also comprises an attenuation amount controller and an attenuator. The attenuation amount controller computes and outputs an insertion attenuation amount that is an attenuation amount for further reducing the power of the echo remainder. The attenuator further reduces the power of the echo remainder by that insertion attenuation amount.
According to this configuration of this invention, in the simplex status, using the noted attenuator, the power of the echo remainder can be forcibly reduced by the insertion attenuation amount, even when the power of the echo remainder cannot be reduced to the level of the noise power due, for example, to large fluctuations in the amplitude of the noise, to fluctuations in the impulse response of the echo path, or to inadequate tap length.
According to another preferable embodiment of this invention, moreover, the echo canceler further comprises an attenuator and an attenuation amount controller such as described below. That is, the attenuation amount controller computes and outputs an insertion attenuation amount for further reducing the power of the echo remainder. With this invention, this attenuation amount controller computes the insertion attenuation amount as the difference between the desired echo attenuation amount output from the desired echo attenuation amount indicator and the echo attenuation amount output from the echo attenuation amount computer. The attenuator further reduces the power of the echo remainder by the insertion attenuation amount.
According to yet another preferable embodiment of this invention, the echo canceler further comprises an attenuator and an attenuation amount controller such as described below. That is, the attenuation amount controller computes and outputs an insertion attenuation amount for further reducing the power of the echo remainder. With this invention, this attenuation amount controller first computes a reception signal/noise ratio that is a logarithmic ratio between the reception signal power and the noise power output by the noise power computer, and then computes the insertion attenuation amount as the difference between that reception signal/noise ratio and the echo attenuation amount output from the echo attenuation amount computer. The attenuator further reduces the power of the echo remainder by the insertion attenuation amount.
According to yet another preferable embodiment of this invention, the echo canceler further comprises an attenuator and an attenuation amount controller such as described below. That is, the attenuation amount controller computes and outputs an insertion attenuation amount for further reducing the power of the echo remainder. With this invention, this attenuation amount controller computes the insertion attenuation amount as the difference between the echo/noise ratio output by the echo/noise ratio computing unit and the echo cancellation amount output by the echo cancellation amount computer. The attenuator further reduces the power of the echo remainder by the insertion attenuation amount.
In embodying this invention, it is preferable that the echo canceler also comprise a tap length controller for lengthening the tap length in the adaptive filter modulus computer when the echo cancellation amount is smaller than the echo/noise ratio.
According to this configuration of this invention, in the simplex status, even in cases where the echo remainder power cannot be reduced to the level of the noise power due to the tap length being inadequate, for example, that tap length is lengthened under the control of the tap length controller, wherefore it can be expected that the power of the echo remainder will be reduced to the level of the noise power.
In embodying this invention, moreover, it is preferable that, when the duplex detector has determined that the call status has been changed from the simplex status to the duplex status, the echo attenuation amount computer, while in that duplex status, estimate the echo attenuation amount during the time of that duplex status, and output that estimated echo attenuation amount to the block length computer.
According to this configuration of this invention, when the duplex detector has determined that the call status has changed from the duplex status to the simplex status, the adaptive filter modulus computer can utilize the estimated block length held by the block length controller during the time of the duplex status.
According to a preferable embodiment of this invention, the echo canceler further comprises an echo loss amount computer that computes an echo loss amount that is the logarithmic ratio between the reception signal power and the echo power. When the duplex detector has determined that the call status has changed from the duplex status to the simplex status, this echo loss amount computer estimates the echo attenuation amount while in this duplex status by taking it to be the sum of the echo loss amount while in the simplex status immediately prior to changing to the duplex status and the echo cancellation amount while in this simplex status. After that, this echo loss amount computer, while in this duplex status, estimates the echo remainder during this duplex status by taking it to be the difference between the reception signal during the duplex status and the estimated echo attenuation amount, and outputs that estimated echo remainder to the echo attenuation amount computer. This echo attenuation amount computer also estimates that the echo attenuation amount during this duplex status is the logarithmic ratio between the reception signal during this duplex status and the estimated echo remainder.
According to this configuration of this invention, while in the duplex status, the echo attenuation amount computer can estimate the block length using the echo remainder estimated by the echo loss amount computer.
According to another preferable embodiment of this invention, when the duplex detector has determined that the call status has changed from the simplex status to the duplex status, the echo attenuation amount computer computes the differential between the pseudo-echo signal power during this duplex status and the reception signal power during this duplex status, while in this duplex status. Then this echo attenuation amount computer estimates the echo attenuation amount during this duplex status by taking it to be the sum of that differential and the echo cancellation amount during the simplex status immediately prior to the change to this duplex status.
According to this configuration of this invention, the echo attenuation amount computer can estimate the block length by itself while in the duplex status.
In embodying this invention, it is preferable that the block length determinator described in the foregoing further comprise a delay register and a first comparator. This delay register, when the duplex detector has determined that the call status is the simplex status, holds the echo attenuation amount output by the echo attenuation amount computer, and outputs it after a delay of a xcex94i sample (where xcex94i is a natural number). The first comparator compares the size relationship between the echo attenuation amount output from this delay register and the echo attenuation amount output from the echo attenuation amount computer.
According to a preferable embodiment of this invention, the block length controller, according to the comparison results produced by the first comparator, either outputs to the adaptive filter modulus computer the block length output by the block length computer without delaying it, or outputs to the adaptive filter modulus computer the block length at a point in time prior to the xcex94i sample held by that block length controller.
According to another preferable embodiment of this invention, the block length determinator further comprises a second delay register that delays the echo attenuation amount output by the first comparator by a xcex94i sample and then outputs it, and a second comparator that compares the size relationship between the echo attenuation amount output from that second delay register and the echo attenuation amount output by the echo attenuation amount computer.
The block length computer noted above may, according to the comparison results produced by the second comparator, output the block length to the block length controller, or, alternatively, output a predetermined initial block length as the block length to the block length controller.
In embodying this invention, it is preferable that, when the noise is made a noise component that excludes the echo component, the block length determinator comprise an echo attenuation amount computer, a desired echo attenuation amount indicator, a block length computer, a delay register, a first comparator, and a block length controller.
The echo attenuation amount computer noted above computes and outputs the echo attenuation amount when the duplex detector has determined that the call status is the simplex status. The desired echo attenuation amount indicator noted above designates the desired echo attenuation amount. The block length computer noted above computes and outputs the block length, based on the echo attenuation amount and the desired echo attenuation amount, so that the echo attenuation amount is made equal to or greater than the desired echo attenuation amount. The delay register noted above holds the echo attenuation amount output by the echo attenuation amount computer, and outputs it after a delay of a xcex94i sample (where xcex94i is a natural number). The first comparator noted above compares the size relationship between the echo attenuation amount output from the delay register and the echo attenuation amount output from the echo attenuation amount computer. The block length controller noted above, according to the comparison results produced by the first comparator, either outputs the block length output by the block length computer to the adaptive filter modulus computer without delaying it, or, alternatively, outputs the block length at a point in time prior to the xcex94i sample (where xcex94i is a natural number), held by that block length controller, to the adaptive filter modulus computer.
Next, the operating method for the echo canceler of the present invention is a method for operating an echo canceler that cancels echoes resulting when part of the reception signal output from the sending party side in a telephone line circles back to the sending party side via an echo path on the receiving party side. The echo canceler operating method of the present invention contains the characteristic process steps described below.
This echo canceler comprises an adaptive filter modulus computing system, an adaptive filter, and an adder, while that adaptive filter modulus computing system comprises a duplex detector, a block length determinator, and an adaptive filter modulus computer.
In this invention, the adaptive filter modulus computing system described above estimates the impulse response of the echo path by the least mean square method, and outputs that estimated impulse response as the adaptive filter modulus. The adaptive filter noted above produces and outputs a pseudo-echo signal for the echo by convoluting the adaptive filter modulus and the reception signal. And the adder noted above cancels the echo by subtracting the pseudo-echo signal from the echo.
Here, the difference between the echo and the pseudo-echo signal is made the echo remainder, the logarithmic ratio between the power of the reception signal and the power of the echo remainder is made the echo attenuation amount, and any predetermined target value for that echo attenuation amount is made the desired echo attenuation amount.
In this invention, the duplex detector noted above determines whether the call status is a simplex status, duplex status, call-transmission status, or non-calling status. When this duplex detector has determined that the call status is the simplex status, the block length determinator noted above determines, and outputs, the block length according to the least mean square method, so that the echo attenuation amount is finally made equal to or greater than the desired echo attenuation amount. After that, the adaptive filter modulus computer noted above computes the adaptive filter modulus using the block length, the echo remainder, and the reception signal, and outputs that adaptive filter modulus to the adaptive filter.
In embodying this invention, it is preferable that the block length determinator noted above comprise an echo attenuation amount computer, a desired echo attenuation amount indicator, an echo cancellation amount computer, an echo/noise ratio computing unit, a block length computer, and a block length controller.
Here, the noise is made a noise component that excludes the echo component, the logarithmic ratio between the echo power and the echo remainder power is made the echo cancellation amount, and the logarithmic ratio between the echo power and the noise power is made the echo/noise ratio.
In this invention, when the duplex detector has determined that the call status is the simplex status, the echo attenuation amount computer noted above computes and outputs the echo attenuation amount. The desired echo attenuation amount indicator noted above designates the desired echo attenuation amount. The echo cancellation amount computer noted above computes and outputs the echo cancellation amount. The block length computer noted above computes, and outputs, the block length so that the echo attenuation amount is made equal to or greater than the desired echo attenuation amount, based on the echo attenuation amount, the desired echo attenuation amount, the echo cancellation amount, and the echo/noise ratio. The block length controller noted above, from the block length, determines the block length to output to the adaptive filter modulus computer, and outputs that block length to the adaptive filter modulus computer.
In embodying this invention, it is preferable that, when the duplex detector has determined that the call status is the simplex status, the block length computer compare the size relationship between the echo attenuation amount and the desired echo attenuation amount in process step A-1.
Process Step A-1-1: When the echo attenuation amount is equal to or greater than the desired echo attenuation amount, this block length computer outputs the block length at the current time to the block length controller, as it is, without updating it.
Process Step A-1-2: When the echo attenuation amount is smaller than the desired echo attenuation amount, on the other hand, this block length computer compares the size relationship between the echo cancellation amount and the echo/noise ratio.
Process Step A-1-2-1: When the echo cancellation amount is smaller than the echo/noise ratio, this block length computer outputs the block length at the current time, as it is, without updating it, to the block length controller.
Process Step A-1-2-2: When the echo cancellation amount is equal to or greater than the echo/noise ratio, on the other hand, if the block length at the current time is less than a predetermined maximum value of the block length, this block length computer increases the block length, and outputs that increased block length to the block length controller. Then it returns to process step A-1. If the block length at the current time is the maximum value for the block length, however, this block length computer outputs the block length at the current time, as it is, without updating it, to the block length controller.
Process Step A-2: Next, the block length controller outputs the block length to the adaptive filter modulus computer.
According to this configuration of this invention, in the simplex status, when the echo attenuation amount is equal to or greater than the desired echo attenuation amount, that echo attenuation amount can be maintained at or higher than the desired echo attenuation amount. In the simplex status, when the echo attenuation amount is smaller than the desired echo attenuation amount, and the echo cancellation amount is smaller than the echo/noise ratio, either the echo attenuation amount can be increased up to the value of the desired echo attenuation amount, or, alternatively, the power of the echo remainder can be decreased down to the level of the noise power. Moreover, in the simplex status, when the echo attenuation amount is smaller than the desired echo attenuation amount, and the echo cancellation amount is equal to or greater than the echo/noise ratio, the echo attenuation amount can be gradually increased up to the value of the desired echo attenuation amount.
Furthermore, in embodying this invention, it is preferable that the echo canceler further comprise an attenuation amount controller and an attenuator. After the processes of process step A-1-2-1, described above, the attenuation amount controller computes and outputs an insertion attenuation amount that is an attenuation amount for further reducing the power of the echo remainder. Then the attenuator further reduces the power of the echo remainder by that insertion attenuation amount.
According to this configuration of this invention, in the simplex status, the power of the echo remainder can be forcibly reduced by this insertion attenuation amount, using this attenuator, even when the echo remainder power cannot be reduced down to the level of the noise power due, for example, to large fluctuations in the noise amplitude, or fluctuations in the impulse response of the echo path, or inadequate tap length.
In embodying this invention, furthermore, it is preferable that the echo canceler further comprise a tap length controller. After the processes in process step A-1-2-1, described earlier, the tap length controller lengthens the tap length in the adaptive filter modulus computer.
According to this configuration of this invention, in the simplex status, even when the echo remainder power cannot be reduced down to the level of the noise power due to insufficient tap length, for example, that tap length is lengthened under the control of the tap length controller, wherefore the power of the echo remainder can be expected to be reduced down to the level of the noise power.
In embodying this invention, it is preferable that the echo canceler further comprise an attenuation amount controller and an attenuator. That attenuation amount controller computes and outputs an insertion attenuation amount that is an attenuation amount for further reducing the power of the echo remainder. The attenuator noted above further reduces the echo remainder power by the insertion attenuation amount output by the attenuation amount controller.
Then, after the tap length in the adaptive filter modulus computer described above has been lengthened by the tap length controller described above, the echo attenuation amount computer compares the size relationship between the echo attenuation amount after the lengthening calculated on the basis of the lengthened tap length and the echo attenuation amount prior to the lengthening calculated on the basis of the tap length prior to lengthening.
After that, when the echo attenuation amount after lengthening is larger than the echo attenuation amount prior to lengthening, this echo attenuation amount computer maintains the lengthening of the tap length in the adaptive filter modulus computer by the tap length controller.
This echo attenuation amount computer, moreover, when the echo attenuation amount after lengthening is equal to or less than the echo attenuation amount prior to lengthening, terminates the lengthening of the tap length in the adaptive filter modulus computer by the tap length controller. Then the attenuation amount controller described earlier computes an insertion attenuation amount, and the attenuator described earlier further reduces the power of the echo remainder by that insertion attenuation amount.
According to this configuration of this invention, after the tap length has been lengthened, confirmation is made as to whether or not the lengthening of the tap length was effective. When the echo attenuation amount after lengthening is larger than the echo attenuation amount prior to lengthening, then the lengthening is shown to have been effective. Accordingly, the lengthening of the tap length is continued. When the echo attenuation amount after lengthening is equal to or less than the echo attenuation amount prior to lengthening, then the lengthening is shown to have been ineffective. In that case, the power of the echo remainder can be forcibly reduced by that insertion attenuation amount by the attenuator described in the foregoing.
In embodying this invention, furthermore, it is preferable that, when the duplex detector has determined that the call status has been changed from the simplex status to the duplex status, the echo cancellation amount computer described earlier estimate the echo cancellation amount immediately prior during the simplex status immediately prior to the change to the duplex status as the echo cancellation amount during the duplex status. The echo/noise ratio computing unit described earlier estimates the echo/noise ratio immediately prior during the simplex status immediately prior to the change to this duplex status as the echo/noise ratio during that duplex status.
Next, during that duplex status, the echo attenuation amount computer described earlier estimates the echo attenuation amount during that duplex status time, and outputs that estimated echo attenuation amount to the block length computer.
Process Step B-1: The block length computer compares the size relationship between the estimated echo attenuation amount and the desired echo attenuation amount output by the desired echo attenuation amount indicator.
Process Step B-1-1: When the estimated echo attenuation amount is equal to or greater than the desired echo attenuation amount, this block length computer outputs the block length at the current time, as is, without updating it, to the block length controller.
Process Step B-1-2: Alternatively, when the estimated echo attenuation amount is smaller than the desired echo attenuation amount, this block length computer compares the size relationship between the estimated echo cancellation amount and the estimated echo/noise ratio.
Process Step B-1-2-1: When the estimated echo cancellation amount is smaller than the estimated echo/noise ratio, this block length computer outputs the block length at the current time, as is, without updating it, to the block length controller.
Process Step B-1-2-2: When, on the other hand, the estimated echo cancellation amount is equal to or greater than the estimated echo/noise ratio, if the block length at the current time is less than the predetermined maximum value of the block length, this block length computer increases the block length, and outputs the increased block length to the block length controller. Then it returns to process step. If, on the other hand, the block length at the current time is the maximum value of the block length, then the block length computer outputs the block length at the current time, as is, without updating it, to the block length controller noted above.
Process Step B-2: Next, the block length controller holds this block length without outputting it to the adaptive filter modulus computer.
The adaptive filter modulus compute r stops the computation of the adaptive filter modulus, also holds t he adaptive filter modulus immediately prior during the simplex status immediately prior to that duplex status, and outputs that adaptive filter modulus to the adaptive filter.
Next, when the duplex detector determines that the call status has been changed from the duplex status to the simplex status, the block length controller outputs the block length held by that block length controller to the adaptive filter modulus computer.
According to this configuration of this invention, when the duplex detector determines that the call status has been change d from the duplex status to the simplex status, the adaptive filter modulus computer can utilize the estimated block length held by the block length controller during the duplex status.
In embodying this invention, it is preferable that, when the logarithmic ratio between the reception signal power and the echo power is defined as the echo loss amount, the block length determinator described earlier comprise an echo loss amount computer for computing that echo loss amount.
When the duplex detector has determined that the call status has been changed from the simplex status to the duplex status, the echo loss amount computer estimates the echo attenuation amount during that duplex status to be the sum of the echo loss amount during the simplex status immediately prior to the change to that duplex status and the echo cancellation amount during that simplex status.
Next, during this duplex status, the echo loss amount computer estimates the echo remainder during that duplex status to be the difference between the reception signal during that duplex status and the estimated echo attenuation amount, and outputs that estimated echo remainder to the echo attenuation amount computer. The echo attenuation amount computer estimates the echo attenuation amount during this duplex status to be the logarithmic ratio between the reception signal during this duplex status and this estimated echo remainder, and outputs that estimated echo attenuation amount to the block length computer.
According to this configuration of this invention, during the duplex status, the echo attenuation amount computer can estimate the block length using the echo remainder estimated by the echo loss amount computer.
In embodying this invention, furthermore, it is preferable that, when the duplex detector has determined that the call status has been changed from the simplex status to the duplex status, during that duplex status, the echo attenuation amount computer described in the foregoing compute the differential between the power of the reception signal during this duplex status and the power of the pseudo-echo signal during the duplex status. Next, this echo attenuation amount computer estimates the echo attenuation amount during this duplex status as the sum of that differential and the echo cancellation amount during the simplex status immediately prior to the change to the duplex status, and outputs that estimated echo attenuation amount to the block length computer.
According to this configuration of this invention, during the duplex status, the echo attenuation amount computer can estimate the block length by itself.
In embodying this invention, furthermore, it is preferable that the block length determinator described earlier further comprise a delay register and a first comparator. Then, when the duplex detector has determined that the call status is the simplex status, the delay register holds the echo attenuation amount output by the echo attenuation amount computer, and outputs it after a delay of a xcex94i sample (where xcex94i is a natural number). Next, the first comparator noted above compares the size relationship between the echo attenuation amount output from the delay register and the echo attenuation amount output from the echo attenuation amount computer.
According to a preferred embodiment of this invention, when the duplex detector has determined that the call status is the simplex status, the block length computer, in process step C-1, compares the size relationship between the echo attenuation amount and the desired echo attenuation amount.
Process Step C-1-1: When the echo attenuation amount is equal to or greater than the desired echo attenuation amount, this block length computer outputs the block length at the current time, as is, without updating it, to the block length controller.
Process Step C-1-2: When the echo attenuation amount is smaller than the desired echo attenuation amount, on the other hand, the block length computer compares the size relationship between the echo cancellation amount and the echo/noise ratio.
Process Step C-1-2-1: When the echo cancellation amount is smaller than the echo/noise ratio, the block length computer outputs the block length at the; current time, as is, without updating it, to the block length controller.
Process Step C-1-2-2: When the echo cancellation amount is equal to or greater than the echo/noise ratio, on the other hand, if the block length at the current time is less than the predetermined maximum value of the block length, the block length computer increases the block length, and outputs that increased block length to the block length controller. After that, it returns to process step C-1. If, on the other hand, the block length at the current time is the maximum value for the block length, then the block length computer outputs the block length at the current time, as is, without updating it, to the block length controller.
Process Step C-2: Next, the block length controller holds the block length output by the block length computer.
Here, the echo attenuation amount output from the delay register is made the delayed echo attenuation amount, and the echo attenuation amount output from the echo attenuation amount computer is made the first undelayed echo attenuation amount.
Process Step C-3: Next, the first comparator compares the size relationship between the first undelayed echo attenuation amount and the delayed echo attenuation amount.
Process Step C-3-1: When the first undelayed echo attenuation amount is judged by the first comparator to be larger than the delayed echo attenuation amount, the first comparator causes the block length controller to output the block length output from the block length computer, without delaying it, to the adaptive filter modulus computer.
Process Step C-3-2: When, on the other hand, the first undelayed echo attenuation amount has been determined by the first comparator to be equal to or less than the delayed echo attenuation amount, the first comparator causes the block length controller to output the block length at a point in time prior to the xcex94i sample held by the block length controller to the adaptive filter modulus computer.
According to this configuration of this invention, in the simplex status, confirmation is made as to whether or not the echo attenuation amount is increasing as time elapses.
When the first undelayed echo attenuation amount is larger than the delayed echo attenuation amount, that is, when the echo attenuation amount at the current time is larger than the echo attenuation amount at a point in time prior to the xcex94i sample, this echo canceler is known to be operating normally. In that case, the first comparator exercises no particular control over the block length controller.
When, on the other hand, the first undelayed echo attenuation amount is equal to or less than the delayed echo attenuation amount, that is, when the echo attenuation amount at the current time is equal to or less than the echo attenuation amount at a point in time prior to the xcex94i sample, it is known that this echo canceler is not operating normally. A possible cause of that would be large noise fluctuation. In that case, the first comparator judges that the echo attenuation amount cannot be reduced any further even though the block length be increased. Thereupon, the block length controller, under the control of the first comparator, outputs the block length at a point in time prior to the xcex94i sample to the adaptive filter modulus computer. After that current point in time, if the large noise fluctuations have ceased, the echo attenuation amount can be expected to again be increased.
In embodying this invention, it is preferable that the block length determinator further comprise a second delay register and a second comparator.
In process step C-3-1, described in the foregoing, the first comparator also outputs the first undelayed echo attenuation amount as the first delayed echo attenuation amount for consideration. And in process step C-3-2, described in the foregoing, the first comparator also outputs the delayed echo attenuation amount as the first delayed echo attenuation amount for consideration.
Next, the second delay register delays the first delayed echo attenuation amount for consideration by the xcex94i sample and outputs it as the second delayed echo attenuation amount for consideration.
Next, the second comparator compares the size relationship between the second delayed echo attenuation amount for consideration output from the second delay register and the echo attenuation amount output by the echo attenuation amount computer. When the echo attenuation amount is judged by the second comparator to be larger than the second delayed echo attenuation amount for consideration, the second comparator does nothing. When, on the other hand, the second comparator judges that the echo attenuation amount is equal to or less than the second delayed echo attenuation amount for consideration, the second comparator outputs a control signal to the block length computer to cause a predetermined initial block length to be output as the block length to the block length controller. At the same time, this second comparator outputs a control signal to the block length controller to cause the initial block length to be output to the adaptive filter modulus computer.
According to this configuration of this invention, it can be verified as to whether returning the block length to the block length at a point in time prior to the xcex94i sample was effective or not.
According to a preferred embodiment of this invention, furthermore, when the duplex detector has determined that the call status is the simplex status, the first comparator, in process step D-1, compares the size relationship between the echo attenuation amount output with a delay of the xcex94i sample from the delay register and the echo attenuation amount output from the echo attenuation amount computer.
Here, the echo attenuation amount output with a delay of the xcex94i sample from the delay register is made the delayed echo attenuation amount, and the echo attenuation amount output from the echo attenuation amount computer is made the first undelayed echo attenuation amount.
Process Step D-1-1: When the first undelayed echo attenuation amount has been judged by the first comparator to be larger than the delayed echo attenuation amount, the first comparator outputs that first undelayed echo attenuation amount as the echo attenuation amount to the block length computer.
Process Step D-1-2: When the first comparator has judged that the first undelayed echo attenuation amount is equal to or less than the delayed echo attenuation amount, on the other hand, the first comparator causes the desired echo attenuation amount indicator to output the desired echo attenuation amount from that desired echo attenuation amount indicator to that first comparator, and then outputs that desired echo attenuation amount as the echo attenuation amount to the block length computer.
Process Step D-2: Next, the block length computer compares the size relationship between the echo attenuation amount output from the first comparator and the desired echo attenuation amount.
Process Step D-2-1: When the echo attenuation amount is equal to or greater than the desired echo attenuation amount, this block length computer outputs the block length at the current time, as is, without updating it, to the block length controller.
Process Step D-2-2: When the echo attenuation amount is smaller than the desired echo attenuation amount, on the other hand, the block length computer compares the size relationship between the echo cancellation amount and the echo/noise ratio.
Process Step D-2-2-1: When the echo cancellation amount is smaller than the echo/noise ratio, this block length computer outputs the block length at the current time, as is, without updating it, to the block length controller.
Process Step D-2-2-2: When the echo cancellation amount is equal to or greater than the echo/noise ratio, on the other hand, if the block length at the current time is less than the predetermined maximum value of the block length, the block length computer increases the block length, and outputs that increased block length to the block length controller. Then it returns to process step D-2. If, however, the block length at the current time is the maximum value of the block length, then the block length computer outputs the block length at the current time, as is, without updating it, to the block length controller.
Process Step D-3: Next, the block length controller outputs that block length to the adaptive filter modulus computer.
According to this configuration of this invention, in the simplex status, confirmation is made as to whether or not the echo attenuation amount is increasing as time elapses.
When the first undelayed echo attenuation amount is larger than the delayed echo attenuation amount, that is, when the echo attenuation amount at the current time is larger than the echo attenuation amount at a point in time prior to the xcex94i sample, it is known that this echo canceler is operating normally. In that case, the first undelayed echo attenuation amount is output from the first comparator to the block length computer. Accordingly, to all appearances, the echo attenuation amount is directly output from the echo attenuation amount computer to the block length computer.
When the first undelayed echo attenuation amount is equal to or less than the delayed echo attenuation amount, on the other hand, that is, when the echo attenuation amount at the current time is equal to or less than the echo attenuation amount at a point in time prior to the xcex94i sample, it is known that this echo canceler is not operating normally. A possible cause thereof is large fluctuation in the noise amplitude. In that case, the first comparator judges that the echo attenuation amount cannot be further reduced even if the block length be increased. Thereupon, the first comparator outputs the desired echo attenuation amount from the desired echo attenuation amount computer to that first comparator, and that desired echo attenuation amount is output as the echo attenuation amount to the block length computer. Accordingly, to all appearances, an echo attenuation amount having the same value as the desired echo attenuation amount is directly output from the echo attenuation amount computer to the block length computer. Hence this block length computer outputs the block length at the current time, without increasing the block length, to the block length controller. This block length controller outputs the block length at this current time to the adaptive filter modulus computer. After that current time, if the large fluctuations in the noise amplitude have ceased, it can be expected that the echo attenuation amount will again be increased.
In embodying this invention, it is preferable that the block length determinator described earlier further comprise a second delay register and a second comparator.
In process step D-1-1, described earlier, when the first comparator judges that the first undelayed echo attenuation amount is larger than the delayed echo attenuation amount, the delayed echo attenuation amount is also output as the first delayed echo attenuation amount for consideration to the second delay register. Furthermore, in process step D-1-2, described earlier, the first comparator, after causing the desired echo attenuation amount to be output from the desired echo attenuation amount indicator to that first comparator, also outputs the delayed echo attenuation amount as the first delayed echo attenuation amount for consideration to the second delay register.
Next, the second delay register outputs the delayed echo attenuation amount, after further delaying it by the xcex94i sample, as the second delayed echo attenuation amount for consideration, to the second comparator.
Next, the second comparator compares the size relationship between the second delayed echo attenuation amount for consideration and the echo attenuation amount output by the echo attenuation amount computer. When this second comparator judges that the echo attenuation amount is larger than the second delayed echo attenuation amount for consideration, that second comparator does nothing. When, however, the second comparator judges that the echo attenuation amount is equal to or less than the second delayed echo attenuation amount for consideration, the second comparator causes the block length computer to output the predetermined initial block length, as the block length, to the block length controller.
According to this configuration of this invention, confirmation is made as to whether or not it was effective to return the block length at the current time to the block length at a point in time prior to the xcex94i sample.
In embodying this invention, moreover, it is preferable, when the difference between the echo attenuation amount and the desired echo attenuation amount in sample number i (where i=1, 2, 3, . . . ) is made Z(i), that the block length be made BL(i), and that the increase in that block length BL(i) be made xcex94BL(i), and, when the duplex detector has determined that the call status is the simplex status, and when the block length computer has determined that the echo attenuation amount input to that block length computer is smaller than the desired echo attenuation amount and that the echo cancellation amount is equal to or greater than the echo/noise ratio, that the block length computer, in accordance with formulas 2 and 2xe2x80x2 given below, increase and compute the block length BL(i) (where INT is an integerizing function, and C1 is either a constant or a function for the ratio between the echo power and the noise power).                                                                                           BL                  ⁢                                      xe2x80x83                                    ⁢                                      (                                          i                      +                      1                                        )                                                  =                                                      BL                    ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                        +                                      Δ                    ⁢                                          xe2x80x83                                        ⁢                    BL                    ⁢                                          xe2x80x83                                        ⁢                                          (                      i                      )                                                                                                                                                                Δ                  ⁢                                      xe2x80x83                                    ⁢                  BL                  ⁢                                      xe2x80x83                                    ⁢                                      (                    i                    )                                                  =                                  INT                  ⁢                                      xe2x80x83                                    ⁢                                      (                                                                  10                                                                              Z                            ⁢                                                          xe2x80x83                                                        ⁢                                                          (                              i                              )                                                                                20                                                                    +                      C1                                        )                                                                                      }                            (        2        )                                                                                                      BL                  ⁢                                      xe2x80x83                                    ⁢                                      (                                          i                      +                      1                                        )                                                  =                                                                            (                                              1.0                        +                                                  Δ                          ⁢                                                      xe2x80x83                                                    ⁢                          BL                          ⁢                                                      xe2x80x83                                                    ⁢                                                      (                            i                            )                                                                                              )                                        ·                    BL                                    ⁢                                      xe2x80x83                                    ⁢                                      (                    i                    )                                                                                                                                            Δ                  ⁢                                      xe2x80x83                                    ⁢                  BL                  ⁢                                      xe2x80x83                                    ⁢                                      (                    i                    )                                                  =                                  INT                  ⁢                                      xe2x80x83                                    ⁢                                      (                                                                  10                                                                              Z                            ⁢                                                          xe2x80x83                                                        ⁢                                                          (                              i                              )                                                                                20                                                                    +                      C1                                        )                                                                                      }                                      (          2          )                xe2x80x2            
According to this configuration of this invention, the block length BL(i) is treated as a Z(i) function. When the echo attenuation amount is sufficiently smaller than the desired echo attenuation amount, that is, when Z(i) is large, the increase xcex94BL(i) in the block length BL(i) is also large, so the block length BL(i) will greatly increase. Accordingly, it is possible to quickly find the optimum block length BL(i) for making the echo attenuation amount approximate the desired echo attenuation amount. Using an echo canceler having a conventional configuration, on the other hand, the block length is increased at a constant ratio (by 1, for example) irrespective of the size of the echo attenuation amount. Accordingly, this invention is able to more quickly find the optimum block length BL(i) for making the echo attenuation amount approximate the desired echo attenuation amount than an echo canceler having a conventional configuration.